Artyom Lazyan

Senior Embedded C/C++ Software Engineer

VadaTech Inc • Vollzeit

May 2022 - Present • 4 yrs 4 mos

Develop cross-platform Qt/C++ applications and engineering tools for system control, power management, diagnostics, and telemetry visualization. Maintain BSPs for embedded platforms based on NXP Layerscape, QorIQ, Intel Arria V, Xilinx ZynqMP, and NVIDIA Jetson Nano, covering the full boot flow from preloader and U-Boot to Linux. Build and customize embedded Linux distributions using Yocto Project and Buildroot for production-ready releases. Develop and debug Linux device drivers and board-level interfaces for peripherals including I2C, SPI, QSPI, UART, PCIe, Ethernet, MMC, and GPIO. Troubleshoot low-level hardware/software integration issues involving bootloader bring-up, device tree configuration, peripheral initialization, and system validation.

Research Scientist

IIAP ( Institute for Informatics and Automated Problems) • Teilzeit

May 2020 - Aug 2026 • 6 yrs 3 mos

Design cloud-native and microservice-based architectures using technologies such as gRPC, Protocol Buffers, real-time telemetry pipelines, and scalable back-end services for distributed drone operations. Develop and maintain a cross-platform C++/Qt platform for UAV swarm mission planning, coordination, and control. Research and implement decentralized swarm coordination algorithms, including Rotor-Router, Gossip/Broadcast protocols, and Eulerian path methods for autonomous navigation, area coverage, and resilient mission execution. Integrate Pixhawk-based UAVs and Raspberry Pi companion computers for live telemetry acquisition, visualization, and control-loop support. Build systems for fault-tolerant telemetry streaming, mission synchronization, and distributed supervisory control across multiple UAV agents. Develop aerial imaging and reconstruction workflows, including panorama generation and environmental/3D scene reconstruction from UAV-captured data.

Software Engineer

AMD • Vollzeit

Mar 2020 - May 2022 • 2 yrs 2 mos

Developed and maintained performance-critical C/C++ components and algorithms for the implementation back end of the Xilinx Vivado Design Suite. Worked on software supporting floorplanning, placement, and routing workflows within FPGA implementation. Analyzed implementation workloads and optimized software algorithms for runtime, memory utilization, scalability, robustness, and Quality of Results. Profiled and debugged complex C++ back-end components to identify algorithmic bottlenecks, memory issues, and architecture-specific software defects. Developed Python automation utilities for internal engineering workflows and design-run analysis. Created Grafana dashboards for performance monitoring, workflow analysis, and data-driven optimization of implementation runs.