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sanjaypuli587

Sanjay P

@sanjaypuli587

FPGA Verilog AXI Stream RTL Design Engineer

Indien
Englisch, Telugu, Hindi
Einige Informationen werden in englischer Sprache angezeigt.
Über mich
I am an FPGA and RTL Design Engineer with hands-on experience in Verilog and AXI Stream based designs. I have worked on packet processing, FIFO design, and debugging complex RTL issues. I focus on writing clean, efficient, and reliable hardware code. I can help with: Verilog / RTL design AXI Stream interfaces FIFO implementation Debugging and fixing design issues I ensure quick response and quality delivery.... Mehr lesen

Kompetenzen

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sanjaypuli587
Sanjay P
offline • 

Meine Dienstleistungen

Programmierung & Technik
I will debug and design verilog fpga rtl axi stream fifo modules
Ab5 $ / ProjektWeitere Details

Arbeitserfahrung

Maven

Hardware engineer

Maven • Vollzeit

Jun 2023 - Present • 2 yrs 11 mos

I am an FPGA and RTL Design Engineer with hands-on experience in Verilog and AXI Stream based designs. I have worked on FIFO design, packet processing, and debugging complex RTL issues. I can help with Verilog coding, AXI interfaces, and fixing design bugs. I am new to Fiverr but committed to delivering high-quality and reliable work.