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Ritesh K
@ritesh_4211
Electrical Engineering Student
Indien
Englisch, Hindi
Über mich
I am an Electrical Engineering student at IIT Ropar with a strong focus on RTL design and digital architectures. I have extensive experience architecting 32-bit RISC-V processors, UART CDC bridges, and complex FSM control systems using Verilog HDL and Xilinx Vivado. I am ranked globally at number one on HDLBits for Verilog design and verification.
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Ritesh K
offline •
Durchschnittliche Antwortzeit: 1 Stunde
Meine Dienstleistungen
Eingebettete Systeme & Internet der Dinge
I will design verilog hdl rtl modules, fsm, fifo and testbench
Portfolio
Arbeitserfahrung
Semiconductor Training Program Participant
Texas Instruments
Jan 2026 - Present • 7 mos
Selected for Texas Instruments’ semiconductor training program. The program covers comprehensive training in analog electronics and semiconductor technologies, focusing on practical applications and industry-standard design methodologies.
