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Poovarasan L
@poovarasanl
Indien
Englisch, Tamil
Über mich
I'm an ECE student with strong skills in Verilog HDL and Digital System Design.
I can design, simulate, and debug combinational and sequential digital circuits such as multiplexers, decoders, adders, counters, flip-flops, and ALUs.
✅ Verilog Coding & Testbench Creation
✅ Simulation using Vivado / ModelSim
✅ Error Debugging & Timing Verification
✅ Well-documented reports and waveform results
I’m passionate about digital logic and HDL-based system design. My goal is to deliver clean, optimized, and well-tested Verilog code for your academic or professional projects.
Kompetenzen
Poovarasan L
offline •
Meine Dienstleistungen
Eingebettete Systeme & Internet der Dinge
I will ai based traffic light controller using verilog hdl and python automation
