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Parth
@parth292000
FPGA RTL Engineer Verilog VHDL Testbench Debugging C Cpp Python
Indien
Englisch
Über mich
I am a Master’s graduate in Integrated Circuits and Systems with hands-on experience in FPGA and digital design. I work with Verilog, VHDL, C, C++, and Python to build and debug reliable solutions. I can design RTL modules, write testbenches, fix simulation issues, and develop clean, synthesizable code. I focus on clear communication, practical solutions, and on-time delivery. Feel free to message me to discuss your project.
Kompetenzen
Parth
offline •
Durchschnittliche Antwortzeit: 1 Stunde
Meine Dienstleistungen
Eingebettete Systeme & Internet der Dinge
I will design and debug verilog or vhdl rtl with testbench
