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Jahnavi Bingi
@jahnavi_bingi
Verilog RTL, FPGA Design Engineer
Indien
Englisch, Telugu, Hindi
Über mich
I am an Electronics and Communication Engineering student focused on Verilog RTL design, FPGA development, and digital system design.
I work with synthesizable Verilog HDL and have hands-on experience developing and verifying digital modules using tools such as Xilinx Vivado. My project experience includes DMA controllers, UART communication, priority queue architectures, and processor-related RTL design.
I can help with RTL module development, FSMs, FIFOs, UART, counters, registers, testbenches, simulation, debugging, and other digital design tasks.
Kompetenzen
Jahnavi Bingi
offline •
Durchschnittliche Antwortzeit: 1 Stunde
Meine Dienstleistungen
Eingebettete Systeme & Internet der Dinge
I will design synthesizable verilog rtl modules
