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Hasnat S
@hasnatsajid208
RTL Design Verification Engineer
Pakistan
Englisch, Urdu
Über mich
I am a digital design engineer with hands-on experience across full-custom RTL, verification, and FPGA integration. I specialize in architecture, self-checking testbenches, and timing closure for projects ranging from legacy system emulation to cryptographic accelerators. I am comfortable owning blocks end-to-end and optimizing for high-performance hardware.
Kompetenzen
Hasnat S
offline •
Meine Dienstleistungen
Eingebettete Systeme & Internet der Dinge
I will design a custom uart, spi, or i2c interface in verilog or systemverilog
Eingebettete Systeme & Internet der Dinge
I will write systemverilog, verilog testbenches and verify your rtl design
Portfolio
Arbeitserfahrung
RTL Design & Verification Engineer
freelance • Freiberufler
Jan 2023 - Present • 3 yrs 9 mos
Digital design engineer providing services across full-custom RTL, verification, and FPGA integration. Responsibilities include cycle-accurate legacy system emulation, cryptographic accelerator design, and owning blocks end-to-end from architecture to timing closure. Experienced in self-checking testbenches, synthesis, and design reviews for short-term contracts and IP blocks.
