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Hasnain Nisar
@hasnainnisarali
FPGA Engineer for RTL Design and UVM Verification
Pakistan
Englisch
Über mich
Welcome to my Digital Design & Verification profile. I am a VLSI/FPGA engineer specializing in front-end RTL Design and Advanced UVM Verification.
Our Expertise:
• RTL Design: Verilog/SystemVerilog, FSMs, FIFOs, custom hardware.
• Verification: UVM-1.2, layered testbenches, SVA, constrained-random testing, coverage closure.
• Protocols: AXI, AHB, APB, SPI, UART, Avalon DMA.
• EDA Tools: Intel Quartus Prime, Questa, ModelSim, QSYS.
I deliver clean, high-quality, and fully verified code for your digital systems. Let's collaborate on your next project!
Kompetenzen
Hasnain Nisar
offline •
Meine Dienstleistungen
Eingebettete Systeme & Internet der Dinge
I will do fpga rtl design in verilog and systemverilog uvm verification
Portfolio
Arbeitserfahrung
Digital IC Design & Verification Trainee
Tech Destination Pakistan • Vollzeit
May 2026 - Present • 5 mos
Selected as a specialized Engineer under the elite National Semiconductor HR Development Programme (NSHRDP - INSPIRE). I engineer high-reliability front-end digital systems and robust verification frameworks. Core Engineering Focus: • Architecture & RTL Design: Developing optimized, synthesizable digital hardware modules, advanced FSM architectures, and custom IP blocks using Verilog and SystemVerilog. • Hardware-Software Co-Design: Building low-latency hardware integration subsystems, FPGA programming, and embedded C firmware stacks for complete system-on-chip evaluation. • System-Level Validation: Practical implementation of high-performance logic networks, computer architecture optimizations, and Design for Test (DFT) structural checks.
