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Avanthika
@avanthikarajend
I will write professional Verilog and VHDL code for your FPGA projects
Indien
Englisch, Tamil
Über mich
Welcome! I specialize in digital logic design using Verilog, VHDL, and SystemVerilog. I transform circuit requirements, block diagrams, and specs into clean, synthesisable RTL code optimized for FPGAs and ASICs.
What I offer:
- Verilog/VHDL RTL design
- Finite State Machines (FSM)
- Testbenches & verification
- Tool support (Vivado, Quartus, EDA Playground)
Every delivery includes fully structured code, inline comments, and documentation. Let's bring your hardware designs to life—send your project specs to get started today!
Kompetenzen
Avanthika
offline •
Durchschnittliche Antwortzeit: 1 Stunde
Meine Dienstleistungen
Eingebettete Systeme & Internet der Dinge
I will write professional verilog and vhdl code for your fpga projects
Illustrationen
I will draw a custom handmade portrait sketch from your photo
Portfolio
Arbeitserfahrung
Freelance FPGA / RTL Design Engineer
Self Employed • Selbstständig
Jun 2024 - Jan 2025 • 7 mos
- Developed and delivered synthesisable RTL code in Verilog and VHDL based on client specifications. - Designed custom combinational logic circuits, multi-bit adders, multiplexers, and decoders. - Constructed robust Finite State Machines (FSM) for sequential control logic and sequence detection. - Wrote functional testbenches to verify digital designs and analyze simulation waveforms. - Utilized industry toolchains including Xilinx Vivado, Intel Quartus Prime, and ModelSim for verification. - Provided clean, well-commented hardware code along with comprehensive design documentation.
