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Anoopraj V
@anoopraj_verma
Vivado FPGA Design RTL Coding Debugging
Indien
Englisch
Über mich
Hey! I’m an RTL Design Engineer with 2+ years of experience in Verilog, SystemVerilog, SVA, and FPGA development using Vivado.
I specialize in writing clean, optimized RTL and SystemVerilog Assertions (SVA) for bug-free, verifiable designs. Whether it’s building a module from scratch or debugging timing issues with ILA/VIO, I’ve got you covered.
🔧 Services:
RTL design & verification
SVA-based assertion writing
Vivado synthesis, implementation & debugging
Testbench creation
I deliver fast, detailed, and well-documented work that fits your exact needs.
Kompetenzen
Anoopraj V
offline •
Durchschnittliche Antwortzeit: 1 Stunde
Meine Dienstleistungen
Eingebettete Systeme & Internet der Dinge
I will fix, debug, or write verilog and systemverilog code
Eingebettete Systeme & Internet der Dinge
I will do rtl verification, uvm testbench , functional coverage for asic and fpga
